999 resultados para Dynamic packaging


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O aparecimento da Internet revolucionou as operações dentro do canal da distribuição turística, obrigando à reavaliação dos intervenientes a nível da forma de actuação e de posicionamento. A distribuição turística transformou-se num dos factores mais críticos para a competitividade dos destinos e das empresas turísticas, uma vez que tem como principal função o tratamento, a combinação e a organização da informação. A Internet permitiu e facilitou o acesso instantâneo à informação turística bem como a efectuar reservas e compras de produtos turísticos. Neste contexto tecnológico, emergiram na World Wide Web sites que permitem ao turista a criação de um pacote personalizado, que apresenta o preço em tempo real, designados por Dynamic Packaging. Neste artigo, apresentamos a sua ligação com os sistemas de informação turísticos, analisando as suas potencialidades e desafios inerentes ao desenvolvimento de uma arquitectura tecnológica, que integra a complexidade e especificidade da informação relacionada com a actividade turística, bem como está sujeita às constantes alterações sofridas pelo sector do turismo, numa sociedade onde todos os dias emergem novas funcionalidades e novos conceitos.

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A indústria do turismo caracteriza-se pela sua heterogeneidade e pelo grande volume de transacções realizadas on-line. Cada vez mais os pequenos operadores turísticos optam por desenvolver os seus pequenos sistemas de reservas, para não terem de estar submetidos ao pagamento de comissões às entidades que gerem os grandes sistemas de informação turística. Devido a este facto, têm surgido um grande número de novas fontes de informação turística na Internet. A proliferação de informação turística torna complexo o planeamento das férias por parte do turista. A implementação de sistemas de integração de informação turística torna-se uma necessidade urgente. Ao mesmo tempo que ajudam o turista no planeamento das férias, também permitem aos operadores implementarem novas estratégias de marketing. Uma destas novas estratégias de marketing passa pela implementação do conceito de “Dynamic Packaging”. O “Dynamic Packaging” permite ao turista, ou ao agente turístico, a construção de pacotes que incluem produtos turísticos escolhidos por este sem qualquer limitação. Aos operadores turísticos, permite a criação de regras de negócio sobre a constituição de um pacote. As regras são depois aplicadas dinamicamente à medida que os pacotes são definidos. A arquitectura SEED define a implementação de um sistema de integração de informação turística. Pretende também disponibilizar a base para a implementação de sistemas que suportem o “Dynamic Packaging”. A integração da informação é realizada através da utilização das tecnologias associadas à Web Semântica. A implementação do “Dynamic Packaging” é suportada pela utilização de motores de inferência que permitem a definição e interpretação de regras semânticas.

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Dammann gratings are well known for their ability to generate arrays of Lmiform-intensity beams from an incoming monochromatic beam. We apply the even-numbered Dammann grating to achieve dynamic optical coupled technology. A 1 x N dynamic optical coupled system is developed by employing two complementary even-numbered Dammann gratings. With this system we can achieve a beam splitter and combiner as a switch between them according to the relative shift between the gratings. Also, this system is a preferable approach in integral packaging. More importantly, this device has the potential to be applied to the splitting of a large array, e.g., 8 x 16 array and 64 x 64 array, which is difficult to be realized with conventional splitting methods. We experimentally demonstrated a 1 x 8 coupler at the wavelength of 1550 nm. Furthermore we analyze the effects of the alignment errors between gratings and the wavelength-dependent error on efficiency and uniformity. The experimental results and the influence of alignment error and wavelength-dependent error are analyzed in detail. (c) 2006 Optical Society of America.

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A SPICE simulation model of a novel cascode switch that combines a high voltage normally-on silicon carbide (SiC) junction field effect transistor (JFET) with a low voltage enhancement-mode gallium nitride field effect transistor (eGaN FET) has been developed, with the aim of optimising cascode switching performance. The effect of gate resistance on stability and switching losses is investigated and optimum values chosen. The effects of stray inductance on cascode switching performance are considered and the benefits of low inductance packaging discussed. The use of a positive JFET gate bias in a cascode switch is shown to reduce switching losses as well as reducing on-state losses. The findings of the simulation are used to produce a list of priorities for the design and layout of wide-bandgap cascode switches, relevant to both SiC and GaN high voltage devices. © 2013 IEEE.

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Self-alignment of soldered electronic components such as flip-chips (FC), ball grid arrays (BGA) and optoelectronic devices during solder reflow is important as it ensures good alignment between components and substrates. Two uncoupled analytical models are presented which provide estimates of the dynamic time scales of both the chip and the solder in the self-alignment process. These predicted time scales can be used to decide whether a coupled dynamic analysis is required for the analysis of the chip motion. In this paper, we will show that for flip-chips, the alignment dynamics can be described accurately only when the chip motion is coupled with the solder motion because the two have similar time-scale values. To study this coupled phenomenon, a dynamic modeling method has been developed. The modeling results show that the uncoupled and coupled calculations result in significantly different predictions. The calculations based on the coupled model predict much faster rates of alignment than those predicted using the uncoupled approach.

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Fueled by increasing human appetite for high computing performance, semiconductor technology has now marched into the deep sub-micron era. As transistor size keeps shrinking, more and more transistors are integrated into a single chip. This has increased tremendously the power consumption and heat generation of IC chips. The rapidly growing heat dissipation greatly increases the packaging/cooling costs, and adversely affects the performance and reliability of a computing system. In addition, it also reduces the processor's life span and may even crash the entire computing system. Therefore, dynamic thermal management (DTM) is becoming a critical problem in modern computer system design. Extensive theoretical research has been conducted to study the DTM problem. However, most of them are based on theoretically idealized assumptions or simplified models. While these models and assumptions help to greatly simplify a complex problem and make it theoretically manageable, practical computer systems and applications must deal with many practical factors and details beyond these models or assumptions. The goal of our research was to develop a test platform that can be used to validate theoretical results on DTM under well-controlled conditions, to identify the limitations of existing theoretical results, and also to develop new and practical DTM techniques. This dissertation details the background and our research efforts in this endeavor. Specifically, in our research, we first developed a customized test platform based on an Intel desktop. We then tested a number of related theoretical works and examined their limitations under the practical hardware environment. With these limitations in mind, we developed a new reactive thermal management algorithm for single-core computing systems to optimize the throughput under a peak temperature constraint. We further extended our research to a multicore platform and developed an effective proactive DTM technique for throughput maximization on multicore processor based on task migration and dynamic voltage frequency scaling technique. The significance of our research lies in the fact that our research complements the current extensive theoretical research in dealing with increasingly critical thermal problems and enabling the continuous evolution of high performance computing systems.

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This dissertation focuses on design challenges caused by secondary impacts to printed wiring assemblies (PWAs) within hand-held electronics due to accidental drop or impact loading. The continuing increase of functionality, miniaturization and affordability has resulted in a decrease in the size and weight of handheld electronic products. As a result, PWAs have become thinner and the clearances between surrounding structures have decreased. The resulting increase in flexibility of the PWAs in combination with the reduced clearances requires new design rules to minimize and survive possible internal collisions impacts between PWAs and surrounding structures. Such collisions are being termed ‘secondary impact’ in this study. The effect of secondary impact on board-level drop reliability of printed wiring boards (PWBs) assembled with MEMS microphone components, is investigated using a combination of testing, response and stress analysis, and damage modeling. The response analysis is conducted using a combination of numerical finite element modeling and simplified analytic models for additional parametric sensitivity studies.